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LTC3219
OPERATION
I 2 C Interface
The LTC3219 is a receive-only (slave) device.
The LTC3219 communicates with a host (master) using
the standard I 2 C 2-wire interface. The Timing Diagram
Write Word Protocol Used by the LTC3219
1 7 1 1 8
1
8
1
1
(Figure 2) shows the timing relationship of the signals on
S Slave Address Wr A *Sub-Address A
Data Byte
A
P**
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources, such as the LTC1694 SMBus accelerator,
are required on these lines.
S = Start Condition, Wr = Write Bit = 0, A = Acknowledge,
P = Stop Condition
*The sub-address uses only the ?rst four bits, D0, D1, D2 and D3
**Stop can be delayed until all of the data registers have been written
SUB-ADDRESS
DATA BYTE
ADDRESS
WR
0
0
1
1
0
1
1
0
S7
S6
S5
S4
S3
S2
S1
S0
7
6
5
4
3
2
1
0
START
STOP
SDA
0
0
1
1
0
1
1
0
ACK
S7
S6
S5
S4
S3
S2
S1
S0 ACK
7
6
5
4
3
2
1
0
ACK
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
3219 FO2
Figure 2. Bit Assignments
SDA
t SU, DAT
t SU, STA
t BUF
SCL
t HD, STA
t LOW
t HIGH
t HD, DAT
t HD, STA
t SP
t SU, STO
3219 F03
START
CONDITION
t r
t f
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 3. Timing Parameters
3219fa
11
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